PHIMO: Compact Model for GAA

A compact model for the gate-all-around (GAA) technology is crucial for the next big wave of CMOS. For the nanosheet GAA, there are new requirements compared to those available models for FinFETs. For this purpose, PHIMO(PHysics Integrated Model)-series compact models are developed. One model, PHIMO-NS, following the classical physics-based modeling approach and archiving the research outputs of Peking University since 2007, integrating various homemade GAA-specific modules, is implemented in SPICE simulators by two EDA vendors. Another model, PHIMO-NN, utilizes the power of our latest fusion modeling technique by fusing device physics with neural networks, which is SPICE-compatible, coded with Verilog-A, and tested with Cadence Virtuoso. While PHIMO-NS is accessible upon requests to EDA vendors, a simplified PHIMO-NS with the fusion technique is also supportive for GAA designs. All the PHIMO models are parameterized with calibrated TCAD simulations.

PKP: PHIMO-enhanced Peking University Predictive PDK

At the center of the PDK is the PHIMO model. The PKP3 PDK is open source, containing technology files for Cadence Virtuoso, decks for design rule check, layout v.s. schematic, and parasitic extractions for the 3nm GAA technology node. Parameterized cells (PCell), a simple standard cell library, and SRAM cell designs are also included. A reminder is that the PDK is provided for academic and research, and the designs are not manufacturable in any foundry. For more details regarding the PHIMO and the PKP, please refer to the associated publications, the design rule manual, and other PDK documentation.

News on PKP3

Version 1.0 is available. Sept. 19, 2025

A PHIMO-NN model powered by the latest fusion modeling technique integrating device physics with tiny neural networks.

The model is verified with calibrated TCAD simulations and globally parameterized for six device flavors (NMOS/PMOS with SVT/LVT/SLVT).

Design rules and techfiles for 3-nm nanosheet GAAFET, including FEOL/MOL/BEOL ground rules, parasitic extraction decks, and complete DRC/LVS verification setup.

A standard-cell library with 50+ logic and sequential cell types across multiple drive strengths, fully characterized with Liberty CCS/NLDM views.

6T SRAM bit-cells (111/112/122 sizing variants) with dedicated layout rules, area scaling trends, and electrical characterization under nanosheet-width sweeps.

End-to-end RTL-to-GDS flow validation on open benchmarks, demonstrating reproducible timing, power, and sign-off with PKP.

Recent Publications

[1] B. Peng, F. Zhang, W. Dai, H. Wu, G. Cheng, R. Wang, M. Chan, L. Zhang, “PHIMO-NN: Compact Modeling by Fusing Device Physics and Neural Networks for One-shot Parameterization,” to appear in IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, DOI: 10.1109/TCAD.2025.3590659

[2] S. Chen, B. Peng, Y. Jiao, Y. Li, L. Zhang, Z. Sun, Y. Xue, Z. Ji, R. Wang, R. Huang, “Self-heating effects of vertical gate-all-around transistors: analysis and modeling,” IEEE Trans. Electron Devices, vol. 71, no. 11, pp. 6478 - 6485, Nov. 2024

[3] B. Peng, Y. Jiao, H. Zhong, Z. Rong, Z. Wang, Y. Xiao, W. Wong, L. Zhang, R. Wang, R. Huang, “Compact modeling of quantum confinements in nanoscale gate-all-around MOSFETs,” Fundamental Research, vol. 4, issue 5, pp. 1306-1313, Sept. 2024

[4] B. Peng, S. Chen, Y. Li, L. Zhang, H. Wu, M. Li, R. Wang, R. Huang, “Modeling the parasitic resistances and capacitances of advanced vertical gate-all-around transistors,” IEEE Trans. Electron Devices, vol. 71, no. 1, pp. 461-467, Jan. 2024.

Citations

A citation of PKP, which is appreciated if you use the PDK in any publication, could go as follows:

PKP3. Available online https://pkp.pkueda.org.cn

If you use the PHIMO-NN model in any publication work, a citation to the following article is appreciated:

B. Peng, F. Zhang, W. Dai, H. Wu, G. Cheng, R. Wang, M. Chan, L. Zhang, “PHIMO-NN: Compact Modeling by Fusing Device Physics and Neural Networks for One-shot Parameterization,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, DOI:10.1109/TCAD.2025.3590659